Chemical-mechanical planarization ("CMP") processes are frequently used to planarize the surface layer of a wafer in the production of ultra-high density integrated circuits. In many current CMP processes, a wafer is exposed to a CMP medium under controlled chemical, pressure, velocity, and temperature conditions. Conventional CMP mediums include polishing pads and slurries, and more specifically, a slurry solution containing small, abrasive particles and reactive chemicals covers a planarizing surface on a polishing pad. The wafer and/or the polishing pad are then moved relative to one another allowing the CMP mediums to remove the surface of the wafer.
CMP processes must consistently and accurately planarize a uniform, planar surface on the wafer at a desired end-point. Several hundred microelectronic devices are typically fabricated on a single wafer by depositing layers of various materials on the wafer, and manipulating the wafer and the other layers of material with photolithographic, etching, and doping processes. In order to manufacture ultra-high density integrated circuits, CMP processes must provide a highly planar surface upon which the geometries of the component parts of the die may be accurately positioned across the full surface of the wafer. Current lithographic techniques, for example, must accurately focus the circuit patterns to within a tolerance of approximately 0.1-0.5 .mu.m. If the surface of the wafer is not highly planar, the circuit pattern may not be sufficiently focused in some areas, resulting in defective devices. Therefore, it is important to consistently and accurately planarize a uniformly planar surface on the wafer.
Current CMP processes, however, do not consistently produce a sufficiently uniform, planar surface all the way across the wafer. The rate at which material is removed from the surface of the wafer (the "polishing rate") affects the uniformity of the resulting surface because it may vary from one area on the wafer to another. The polishing rate may vary across the face of the wafer for several reasons, some of which are as follows: (1) the difference in relative velocity between the surface of the wafer and the polishing pad from the center of the wafer to its edge; (2) the difference in slurry distribution and flow rates across the surface of the wafer; (3) any variance in the composition of the material across the wafer; (4) the degree of non-uniformity of the typography of the wafer; (5) the face of the wafer and the surface of the polishing pad may not be parallel with each other throughout the CMP process; (6) the slurry temperature varies across the face of the wafer; and (7) the condition of the polishing pad changes reducing the polishing pad uniformity. Accordingly, since the polishing rate of a wafer may vary from one region of the wafer to another, current CMP processes do not consistently produce a sufficiently planar surface on the resulting wafer.
One relatively new aspect of CMP processing for improving the uniformity and planarity of the surface of wafers is the stop-on-feature wafer design. In a typical SOF wafer, a first layer of material is deposited over the wafer substrate and the features that are fabricated on the substrate, and a second layer of material is deposited over the first layer. The first layer is made from a material that has a relatively low polishing rate, while the second layer is made from a material that has a relatively high polishing rate. In operation, the second layer is planarized until the first layer is exposed. Since the first layer has a lower polishing rate than that of the second layer, any high regions of the second layer will be removed faster than the exposed portions of the first layer. The SOF design, therefore, enhances the uniformity and planarity of the wafer surface because it allows the CMP process to remove the high points along the wafer faster than the low points.
One problem with planarizing an SOF wafer with current CMP oxide processes is that the resulting surface on the wafer is still not sufficiently uniformly planar for some microelectronic devices. Conventional CMP processes, for example, generally produce a finished surface on an SOF wafer with step heights of 2000 .ANG.-3000 .ANG. at the interfaces between the materials of the first and second layers. The planarized surface of an SOF wafer may not be sufficiently uniform because current CMP processes rely primarily on the mechanical abrasiveness of the polishing pad and the particles in the slurry to remove material from the wafer; some regions of the first layer will accordingly be exposed before other regions when the surface of the wafer and the surface of the polishing pad are not parallel to each other, or the slurry is not distributed evenly under the wafer.
Another problem with planarizing SOF wafers with conventional CMP processes is that polishing pad uniformity decreases such that the removal rate varies significantly from one area on the pad to another. Since the first layer is hard, initially exposed two-component areas on the wafer abrade localized areas on the pad causing the pad to have high removal rates in localized areas. Conversely, the soft second layer on the wafer glazes the pad in other areas causing the pad to have low removal rates over the glazed areas. Thus, conventional SOF wafer planarization causes a large divergence in polishing pad uniformity that reduces the planarity of the finished wafers.
Conventional CMP processes attempt to reduce the step heights on SOF wafers by using selective slurries that chemically remove the second layer of material at a faster rate than the first layer of material. In order to increase throughput, conventional CMP processes also use high relative velocities between the pad and wafer, and high temperatures at the pad-wafer interface. The selectivity of the slurry, however, is reduced at higher temperatures because heat causes chemicals in the slurry to react more aggressively with the material of the first layer. Thus, even when the slurry is selective to the second layer, the finished surface will have low points at the initially exposed regions of the first layer. Additionally, because portions of the first layer are now exposed, nonuniformities are introduced to the polishing pad during the polishing cycle that result in uneven polishing of non-exposed areas.
Accordingly, it would be desirable to develop a CMP process that: (1) reduces the amount of material removed from the initially exposed regions of the first layer; (2) still allows material to be rapidly planarized from the second dielectric layer; and (3) minimizes the effect that the exposed parts of the first layer have on the polishing pad and the simultaneous polishing of the second layer.